package bus
import chisel3._

/**
 * 一生一芯命名接口： 学号20210718
 */
class ysyxAXI4 extends Bundle {
  // addr read
  val arready = Input(Bool())
  val arvalid = Output(Bool())
  val araddr = Output(UInt(32.W))
  val arid = Output(UInt(4.W))
  val arlen = Output(UInt(8.W))
  val arsize = Output(UInt(3.W))
  val arburst = Output(UInt(2.W))
  // data read
  val rready = Output(Bool())
  val rvalid = Input(Bool())
  val rresp = Input(UInt(2.W))
  val rdata = Input(UInt(64.W))
  val rlast = Input(Bool())
  val rid = Input(UInt(4.W))
  // addr write
  val awready = Input(Bool())
  val awvalid = Output(Bool())
  val awaddr = Output(UInt(32.W))
  val awid = Output(UInt(4.W))
  val awlen = Output(UInt(8.W))
  val awsize = Output(UInt(3.W))
  val awburst = Output(UInt(2.W))
  // data write
  val wready = Input(Bool())
  val wvalid = Output(Bool())
  val wdata = Output(UInt(64.W))
  val wstrb = Output(UInt(8.W))
  val wlast = Output(Bool())
  // write response
  val bready = Output(Bool())
  val bvalid = Input(Bool())
  val bresp = Input(UInt(2.W))
  val bid = Input(UInt(4.W))

}
